1. Field of the Invention
The invention relates generally to electronic circuitry for use in data communication systems. More particularly, it relates to a DAC audio system and a method for clock mode determination utilizing SCLK auto-detection and generation circuitry at a serial port in which the number of input pins on an integrated circuit is reduced.
2. Description of the Prior Art
As is generally known, there has been a tremendous amount of growth in the area of electronic circuitry used for data communication systems. These communication systems are frequently used to transmit data and clock signals from a first integrated circuit chip to a second integrated circuit chip. However, due to different design applications, there have been an advent of digital audio signals in various formats, such as I2S and TDM formats. The I2S and TDM formats are two different audio input formats which are commonly used to carry a stereo signal (i.e., a left channel and a right channel). Because of the differences in the way that the data are formatted/encoded, the data in the I2S signals cannot be processed in the same manner that the TDM signals are processed.
In order to be competitive in today's marketplace, digital audio systems must be designed so as to accommodate efficiently the processing of audio inputs in multiple data sampling rate frequencies and/or input formats. While it is possible to design on a single integrated circuit chip the capability of handling or processing of different sampling rates or multiple input formats, this design has typically required the need of additional external circuitry as well as the provision of increased input pins onto the integrated circuit chip. Since an increase in the pin count on the integrated circuit chip will cause both complexities in circuit board design and higher manufacturing and assembly cost, this would generally not be a realistic solution due to the fact that input/output pins are a valuable commodity where space limitations are very critical.
The above-mentioned TDM format is one form of compressed audio data which can be converted to PCM (Pulse-Code Modulated) data with a digital audio receiver chip. The conventional standard PCM data includes a high rate, external master input clock signal MCLK; a left-right input clock signal LRCK, which is used to select between the left and right audio channel data; a serial audio data input signal SDIN containing signal information at the MCLK rate; and a serial input clock signal SCLK, which times the transfer of individual bits of the samples of serial audio data.
FIG. 1 is a block diagram of a traditional DAC (digital-to-analog) audio system 100 suitable for illustrating one of the prior art systems. In particular, the audio system 100 includes a digital signal processor (DSP) 102 which forms a part of digital audio source, such as a CD player or digital audio tape player. The DSP 102 provides four signals to an audio DAC (digital-to-analog converter) 104 which consists of a master clock signal MCLK on line 108; an input data signal SDIN on line 110, which are the actual sample values to be reproduced at the audio outputs; a left-right clock LRCK on line 112, which alternates between an indication that the input data belongs to the left channel or to the right channel; and a serial clock SCLK on line 114, which is used to write the input data SDIN into a receiving buffer.
The three signals LRCK, SCLK and SDIN from the DSP 102 are connected to a digital interpolation filter and delta-sigma modulator block 116 via a serial input port 106. The signal MCLK is connected directly to the modulator block 116 of the audio DAC 104. The resulting analog (audio) signal from the modulator block 116 is fed to an analog driver block 118 for further processing on an analog output line 120. This traditional audio system 100 suffers from the drawback of using a high number of input pins, which increases manufacturing cost and adds complexity to circuit board design.
FIG. 2 is a block diagram of another prior art DAC audio system 200. The audio system 200 includes a DSP 202 which provides three signals to an audio DAC 204. The three signals LRCK, SCLK and SDIN on respective lines 212, 214 and 210 are connected from the DSP 202 to a digital interpolation filter and delta-sigma modulator block 216 of the audio DAC 204 via a serial input port 206. The signal LRCK on line 212 is also connected to the modulator block 216 via a PLL (phase-locked loop) block 222.
The PLL block 222 receives the signal LRCK on line 224 and multiples the same by a predetermined factor in order to generate a phase-locked loop output signal PLLOUT corresponding to a master clock mclk on line 226. The resulting analog (audio) signal from the modulator block 216 is fed to an analog driver block 218 for further processing on an analog output line 220. This technique of using a PLL block for generating a master clock mclk is illustrated and described in the aforementioned U.S. Ser. No. 11/427,910. While this audio system 200 has reduced the number of input pins over the one in FIG. 1, it has the disadvantage in that an external serial input clock signal SCLK is still required to be used.
FIG. 3 is a block diagram of still another prior art DAC audio system 300. The audio system 300 is quite similar to the system 100 of FIG. 1. Specifically, the audio system 300 includes a DSP 302 which provides four signals to an audio DAC 304. These four signals MCLK, SCLK, LRCK and SDIN on respective lines 308, 314, 312 and 310 are connected from the DSP 302 to a digital interpolation filter and delta-sigma modulator block 316 of the audio DAC 304 via a divider network 324 and a serial input port 306. The signal MCLK on the line 308 is also connected directly to the modulator block 316. The audio system 300 suffers from the disadvantage that once the external SCLK mode is latched, it cannot be switched back to an internal SCLK mode. Since it uses a simple divider for dividing down the master clock MCLK in order to generate the serial clock SCLK, the edge may be inaccurate with respect to the input data SDIN. Further, this audio system 300 has the problem that it does not support the TDM (time-division-multiplexing) mode of operation.
The prior art DAC audio system 300 of FIG. 3 has been manufactured as an integrated circuit chip and is commercially available from Cirrus Logic, Inc. of Austin, Tex. under their Part No. CS4434/5/8/9. The I.C. chip is a complete, stereo DAC output system which includes interpolation, 1-bit D/A conversion, and output analog filtering in an 8-pin package.
In order to address the problem of increased pin-count on the integrated circuit chip, the inventors of the present invention have developed SCLK auto-detection and generation circuitry for use at a serial input port in a DAC audio system which has a reduced number of pin-count by eliminating the need for inputting the master input clock signal MCLK and/or the serial input clock signal SCLK.
Accordingly, it would therefore be desirable to provide new and novel SCLK auto-detection and generation circuitry for use at a serial port in a DAC audio system which has a reduced number of pin-count and safe data capture. This is achieved without the use of a master input clock signal and/or a serial input clock signal so as to reduce the number of input pins on the integrated circuit chip. It would also be expedient to detect which of several possible modes of operation at the serial port is being received when an internally-generated serial clock signal is to be outputted.